jEdit example source code file (verilog.xml)

This example jEdit source code file (verilog.xml) is included in the DevDaily.com "Java Source Code Warehouse" project. The intent of this project is to help you "Learn Java by Example" ^TM.

Java - jEdit tags/keywords

function, function, keyword1, keyword1, keyword2, keyword3, keyword3, keywords, operator, property, seq, seq, type, value

The jEdit verilog.xml source code

<?xml version="1.0"?>

<!DOCTYPE MODE SYSTEM "xmode.dtd">

<!-- Written By: Wojciech Stryjewski - thvortex@sourceforge.net -->

<MODE>
	<PROPS>
		<!-- Rules for indenting:
		   - Case expressions (a line ending with colon) are indented
		   - Keywords begin, module, task, etc. always indented
		   - Keywords if, while, etc. indent only if ; not on the same line
		-->
		<PROPERTY NAME="indentNextLines" VALUE="(.*:\s*)|(\s*(begin|fork|task|table|specify|primitive|module|generate|function|case[xz]?)\b.*)|(\s*(always|if|else|for|forever|initial|repeat|while)\b[^;]*)" />

		<PROPERTY NAME="commentStart" VALUE="/*" />
		<PROPERTY NAME="commentEnd" VALUE="*/" />
		<PROPERTY NAME="lineComment" VALUE="//" />
		<PROPERTY NAME="noWordSep" VALUE="_'" />
		<PROPERTY NAME="wordBreakChars" VALUE=",+-=<>/?^&*" />
	</PROPS>
	<RULES IGNORE_CASE="FALSE" HIGHLIGHT_DIGITS="TRUE"
		DIGIT_RE="([\p{Digit}]|_)+" NO_WORD_SEP="'">
		<!-- Comments -->
		<SPAN TYPE="COMMENT1">
			<BEGIN>/*
			<END>*/
		</SPAN>
		<EOL_SPAN TYPE="COMMENT2">//

		<!--String Literals -->
		<SPAN TYPE="LITERAL1" ESCAPE="\" NO_LINE_BREAK="FALSE">
			<BEGIN>"
			<END>"
		</SPAN>

		<SEQ TYPE="DIGIT">'d
		<SEQ TYPE="DIGIT">'h
		<SEQ TYPE="DIGIT">'b
		<SEQ TYPE="DIGIT">'o

		<!-- Function calls, module instantiation, system tasks with args -->
		<MARK_PREVIOUS TYPE="FUNCTION" MATCH_TYPE="OPERATOR">(
		<SEQ TYPE="OPERATOR">)

		<!-- Operators -->
		<SEQ TYPE="OPERATOR">=
		<SEQ TYPE="OPERATOR">!
		<SEQ TYPE="OPERATOR">+
		<SEQ TYPE="OPERATOR">-
		<SEQ TYPE="OPERATOR">/
		<SEQ TYPE="OPERATOR">*
		<SEQ TYPE="OPERATOR">>
		<SEQ TYPE="OPERATOR"><
		<SEQ TYPE="OPERATOR">%
		<SEQ TYPE="OPERATOR">&
		<SEQ TYPE="OPERATOR">|
		<SEQ TYPE="OPERATOR">^
		<SEQ TYPE="OPERATOR">~
		<SEQ TYPE="OPERATOR">}
		<SEQ TYPE="OPERATOR">{

		<KEYWORDS>
			<!-- Regular Keywords -->
			<KEYWORD1>always
			<KEYWORD1>assign
			<KEYWORD1>begin
			<KEYWORD1>case
			<KEYWORD1>casex
			<KEYWORD1>casez
			<KEYWORD1>default
			<KEYWORD1>deassign
			<KEYWORD1>disable
			<KEYWORD1>else
			<KEYWORD1>end
			<KEYWORD1>endcase
			<KEYWORD1>endfunction
			<KEYWORD1>endgenerate
			<KEYWORD1>endmodule
			<KEYWORD1>endprimitive
			<KEYWORD1>endspecify
			<KEYWORD1>endtable
			<KEYWORD1>endtask
			<KEYWORD1>for
			<KEYWORD1>force
			<KEYWORD1>forever
			<KEYWORD1>fork
			<KEYWORD1>function
			<KEYWORD1>generate
			<KEYWORD1>if
			<KEYWORD1>initial
			<KEYWORD1>join
			<KEYWORD1>macromodule
			<KEYWORD1>module
			<KEYWORD1>negedge
			<KEYWORD1>posedge
			<KEYWORD1>primitive
			<KEYWORD1>repeat
			<KEYWORD1>release
			<KEYWORD1>specify
			<KEYWORD1>table
			<KEYWORD1>task
			<KEYWORD1>wait
			<KEYWORD1>while

			<!-- Compiler Directives -->
			<KEYWORD2>`include
			<KEYWORD2>`define
			<KEYWORD2>`undef
			<KEYWORD2>`ifdef
			<KEYWORD2>`ifndef
			<KEYWORD2>`else
			<KEYWORD2>`endif
			<KEYWORD2>`timescale
			<KEYWORD2>`resetall
			<KEYWORD2>`signed
			<KEYWORD2>`unsigned
			<KEYWORD2>`celldefine
			<KEYWORD2>`endcelldefine
			<KEYWORD2>`default_nettype
			<KEYWORD2>`unconnected_drive
			<KEYWORD2>`nounconnected_drive
			<KEYWORD2>`protect
			<KEYWORD2>`endprotect
			<KEYWORD2>`protected
			<KEYWORD2>`endprotected
			<KEYWORD2>`remove_gatename
			<KEYWORD2>`noremove_gatename
			<KEYWORD2>`remove_netname
			<KEYWORD2>`noremove_netname
			<KEYWORD2>`expand_vectornets
			<KEYWORD2>`noexpand_vectornets
			<KEYWORD2>`autoexpand_vectornets

			<!-- Type Declaration Keywords -->
			<KEYWORD3>integer
			<KEYWORD3>reg
			<KEYWORD3>time
			<KEYWORD3>realtime
			<KEYWORD3>defparam
			<KEYWORD3>parameter
			<KEYWORD3>event
			<KEYWORD3>wire
			<KEYWORD3>wand
			<KEYWORD3>wor
			<KEYWORD3>tri
			<KEYWORD3>triand
			<KEYWORD3>trior
			<KEYWORD3>tri0
			<KEYWORD3>tri1
			<KEYWORD3>trireg
			<KEYWORD3>vectored
			<KEYWORD3>scalared
			<KEYWORD3>input
			<KEYWORD3>output
			<KEYWORD3>inout

			<!-- Signal Strengths -->
			<KEYWORD3>supply0
			<KEYWORD3>supply1
			<KEYWORD3>strong0
			<KEYWORD3>strong1
			<KEYWORD3>pull0
			<KEYWORD3>pull1
			<KEYWORD3>weak0
			<KEYWORD3>weak1
			<KEYWORD3>highz0
			<KEYWORD3>highz1
			<KEYWORD3>small
			<KEYWORD3>medium
			<KEYWORD3>large

			<!-- System Tasks With No/Optional Arguments -->
			<FUNCTION>$stop
			<FUNCTION>$finish
			<FUNCTION>$time
			<FUNCTION>$stime
			<FUNCTION>$realtime
			<FUNCTION>$settrace
			<FUNCTION>$cleartrace
			<FUNCTION>$showscopes
			<FUNCTION>$showvars
			<FUNCTION>$monitoron
			<FUNCTION>$monitoroff
			<FUNCTION>$random
			<FUNCTION>$printtimescale
			<FUNCTION>$timeformat

			<!-- Built-in primitives -->
			<FUNCTION>and
			<FUNCTION>nand
			<FUNCTION>or
			<FUNCTION>nor
			<FUNCTION>xor
			<FUNCTION>xnor
			<FUNCTION>buf
			<FUNCTION>bufif0
			<FUNCTION>bufif1
			<FUNCTION>not
			<FUNCTION>notif0
			<FUNCTION>notif1
			<FUNCTION>nmos
			<FUNCTION>pmos
			<FUNCTION>cmos
			<FUNCTION>rnmos
			<FUNCTION>rpmos
			<FUNCTION>rcmos
			<FUNCTION>tran
			<FUNCTION>tranif0
			<FUNCTION>tranif1
			<FUNCTION>rtran
			<FUNCTION>rtranif0
			<FUNCTION>rtranif1
			<FUNCTION>pullup
			<FUNCTION>pulldown
		</KEYWORDS>
	</RULES>
</MODE>