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jEdit example source code file (vhdl.xml)
The jEdit vhdl.xml source code<?xml version="1.0"?> <!-- contributed by M. Cesar R. Lacruz (mcesar@sec.upm.es) v1.1 2008/08/29 from previous work by Dante Fabrizio and Nitsan Vardi --> <!DOCTYPE MODE SYSTEM "xmode.dtd"> <MODE> <PROPS> <PROPERTY NAME="label" VALUE="VHDL" /> <PROPERTY NAME="lineComment" VALUE="--" /> </PROPS> <RULES IGNORE_CASE="TRUE"> <!-- string --> <SPAN_REGEXP TYPE="LITERAL4" AT_WORD_START="TRUE" NO_LINE_BREAK="TRUE"> <BEGIN>[box]?" <END>" </SPAN_REGEXP> <SPAN_REGEXP TYPE="LITERAL4" AT_WORD_START="TRUE" NO_LINE_BREAK="TRUE"> <BEGIN>[box]?% <END>% </SPAN_REGEXP> <!-- char --> <SEQ_REGEXP TYPE="LITERAL1" HASH_CHAR="'">(?:'[\x20-\x7e\xa0-\xff]') <!-- predefined attribute --> <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'left\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'right\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'low\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'high\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'ascending\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'image\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'value\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'pos\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'val\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'succ\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'pred\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'leftof\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'rightof\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'base\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'delayed\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'stable\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'quiet\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'transaction\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'event\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'active\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'last_event\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'last_active\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'last_value\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'driving\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'driving_value\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'range\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'reverse_range\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'length\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'simple_name\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'path_name\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'instance_name\b <SEQ_REGEXP TYPE="KEYWORD3" HASH_CHAR="'">'foreign\b <!-- other attribute --> <MARK_FOLLOWING TYPE="KEYWORD4" MATCH_TYPE="KEYWORD3">' <!-- comment --> <EOL_SPAN TYPE="COMMENT1">-- <!-- label --> <!-- sorry, but 'label : component_name', 'label : procedure_name' & 'label : variable :=' are not managed, as they collide with 'generic_name : generic_type' --> <SEQ_REGEXP TYPE="LABEL" AT_WHITESPACE_END="TRUE">(\w|\w[\w\d_]*[\w\d])\s*(?=:)(?!:=)(?!:\s*\d)(?=:\s*(if\b|case\b|while\b|for\b|loop\b|next\b|null\b|block\b|process\b|wait\b|postponed\b|assert\b|with\b|entity\b|component\b|configuration\b|exit\b|return\b|(?:(?:\w[\w\d_]*\w|\w)\s*<=))) <!-- operator --> <SEQ TYPE="OPERATOR">( <SEQ TYPE="OPERATOR">) <SEQ TYPE="OPERATOR">=> <SEQ TYPE="OPERATOR">** <SEQ TYPE="OPERATOR">:= <SEQ TYPE="OPERATOR">/= <SEQ TYPE="OPERATOR">>= <SEQ TYPE="OPERATOR"><= <SEQ TYPE="OPERATOR"><> <SEQ TYPE="OPERATOR">= <SEQ TYPE="OPERATOR">: <SEQ TYPE="OPERATOR">> <SEQ TYPE="OPERATOR">< <SEQ TYPE="OPERATOR">+ <SEQ TYPE="OPERATOR">- <SEQ TYPE="OPERATOR">/ <SEQ TYPE="OPERATOR">* <SEQ TYPE="OPERATOR">& <SEQ TYPE="OPERATOR">| <!-- number --> <SEQ_REGEXP TYPE="DIGIT" AT_WORD_START="TRUE" >\d{1,2}#(?:(?:[\da-f][\da-f_]*\.?[\da-f_]*[\da-f])|[\da-f])#(?:e[+-]?(?:\d[\d_]*\d|\d))?</SEQ_REGEXP> <SEQ_REGEXP TYPE="DIGIT" AT_WORD_START="TRUE" >\d{1,2}:(?:(?:[\da-f][\da-f_]*\.?[\da-f_]*[\da-f])|[\da-f]):(?:e[+-]?(?:\d[\d_]*\d|\d))?</SEQ_REGEXP> <SEQ_REGEXP TYPE="DIGIT" AT_WORD_START="TRUE" >(?:(?:\d[\d_]*\.?[\d_]*\d)|\d)(?:e[+-]?(?:\d[\d_]*\d|\d))?</SEQ_REGEXP> <KEYWORDS> <!-- VHDL-87 keyword --> <KEYWORD1>access <KEYWORD1>after <KEYWORD1>alias <KEYWORD1>all <KEYWORD1>architecture <KEYWORD1>array <KEYWORD1>assert <KEYWORD1>attribute <KEYWORD1>begin <KEYWORD1>block <KEYWORD1>body <KEYWORD1>buffer <KEYWORD1>bus <KEYWORD1>case <KEYWORD1>component <KEYWORD1>configuration <KEYWORD1>constant <KEYWORD1>disconnect <KEYWORD1>downto <KEYWORD1>else <KEYWORD1>elsif <KEYWORD1>end <KEYWORD1>entity <KEYWORD1>exit <KEYWORD1>file <KEYWORD1>for <KEYWORD1>function <KEYWORD1>generate <KEYWORD1>generic <KEYWORD1>guarded <KEYWORD1>if <KEYWORD1>in <KEYWORD1>inout <KEYWORD1>is <KEYWORD1>label <KEYWORD1>library <KEYWORD1>linkage <KEYWORD1>loop <KEYWORD1>map <KEYWORD1>new <KEYWORD1>next <KEYWORD1>null <KEYWORD1>of <KEYWORD1>on <KEYWORD1>open <KEYWORD1>others <KEYWORD1>out <KEYWORD1>package <KEYWORD1>port <KEYWORD1>procedure <KEYWORD1>process <KEYWORD1>range <KEYWORD1>record <KEYWORD1>register <KEYWORD1>report <KEYWORD1>return <KEYWORD1>select <KEYWORD1>severity <KEYWORD1>signal <KEYWORD1>subtype <KEYWORD1>then <KEYWORD1>to <KEYWORD1>transport <KEYWORD1>type <KEYWORD1>units <KEYWORD1>until <KEYWORD1>use <KEYWORD1>variable <KEYWORD1>wait <KEYWORD1>when <KEYWORD1>while <KEYWORD1>with <!-- VHDL-93 new keyword --> <KEYWORD1>group <KEYWORD1>impure <KEYWORD1>inertial <KEYWORD1>literal <KEYWORD1>postponed <KEYWORD1>pure <KEYWORD1>reject <KEYWORD1>shared <KEYWORD1>unaffected <!-- VHDL-2001 new keyword --> <KEYWORD1>protected <!-- VHDL-87 keyword, but shown as operator --> <OPERATOR>abs <OPERATOR>and <OPERATOR>mod <OPERATOR>nand <OPERATOR>nor <OPERATOR>not <OPERATOR>or <OPERATOR>rem <OPERATOR>xor <!-- VHDL-93 new keyword, but shown as operator --> <OPERATOR>rol <OPERATOR>ror <OPERATOR>sll <OPERATOR>srl <OPERATOR>sla <OPERATOR>sra <OPERATOR>xnor <!-- VHDL-87 keyword, but shown as function --> <FUNCTION>deallocate <!-- built-in & standard type --> <KEYWORD2>bit <KEYWORD2>bit_vector <KEYWORD2>boolean <KEYWORD2>character <KEYWORD2>delay_length <FUNCTION>now <FUNCTION>file_open <FUNCTION>file_close <FUNCTION>read <FUNCTION>write <FUNCTION>endfile <KEYWORD2>file_open_kind <KEYWORD2>file_open_status <KEYWORD2>integer <KEYWORD2>natural <KEYWORD2>positive <KEYWORD2>real <KEYWORD2>severity_level <KEYWORD2>string <KEYWORD2>time <!-- boolean --> <LITERAL1>false <LITERAL1>true <!-- char, only those not having a ' ' representation --> <LITERAL1>nul <LITERAL1>soh <LITERAL1>stx <LITERAL1>etx <LITERAL1>eot <LITERAL1>enq <LITERAL1>ack <LITERAL1>bel <LITERAL1>bs <LITERAL1>ht <LITERAL1>lf <LITERAL1>vt <LITERAL1>ff <LITERAL1>cr <LITERAL1>so <LITERAL1>si <LITERAL1>dle <LITERAL1>dc1 <LITERAL1>dc2 <LITERAL1>dc3 <LITERAL1>dc4 <LITERAL1>nak <LITERAL1>syn <LITERAL1>etb <LITERAL1>can <LITERAL1>em <LITERAL1>sub <LITERAL1>esc <LITERAL1>fsp <LITERAL1>gsp <LITERAL1>rsp <LITERAL1>usp <LITERAL1>del <LITERAL1>c128 <LITERAL1>c129 <LITERAL1>c130 <LITERAL1>c131 <LITERAL1>c132 <LITERAL1>c133 <LITERAL1>c134 <LITERAL1>c135 <LITERAL1>c136 <LITERAL1>c137 <LITERAL1>c138 <LITERAL1>c139 <LITERAL1>c140 <LITERAL1>c141 <LITERAL1>c142 <LITERAL1>c143 <LITERAL1>c144 <LITERAL1>c145 <LITERAL1>c146 <LITERAL1>c147 <LITERAL1>c148 <LITERAL1>c149 <LITERAL1>c150 <LITERAL1>c151 <LITERAL1>c152 <LITERAL1>c153 <LITERAL1>c154 <LITERAL1>c155 <LITERAL1>c156 <LITERAL1>c157 <LITERAL1>c158 <LITERAL1>c159 <!-- severity_level --> <LITERAL1>note <LITERAL1>warning <LITERAL1>error <LITERAL1>failure <!-- file_open_kind --> <LITERAL1>read_mode <LITERAL1>write_mode <LITERAL1>append_mode <!-- file_open_status --> <LITERAL1>open_ok <LITERAL1>status_error <LITERAL1>name_error <LITERAL1>mode_error <!-- ieee.std_logic_1164 --> <KEYWORD2>std_logic <KEYWORD2>std_ulogic <KEYWORD2>std_logic_vector <KEYWORD2>std_ulogic_vector <KEYWORD2>x01 <KEYWORD2>x01z <KEYWORD2>ux01 <KEYWORD2>ux01z <FUNCTION>to_bit <FUNCTION>to_bitvector <FUNCTION>to_stdulogic <FUNCTION>to_stdlogicvector <FUNCTION>to_stdulogicvector <FUNCTION>to_x01 <FUNCTION>to_x01z <FUNCTION>to_ux01 <FUNCTION>rising_edge <FUNCTION>falling_edge <FUNCTION>is_x <!-- ieee.numeric_std --> <KEYWORD2>signed <KEYWORD2>unsigned <FUNCTION>shift_left <FUNCTION>shift_right <FUNCTION>rotate_left <FUNCTION>rotate_right <FUNCTION>resize <FUNCTION>std_match <FUNCTION>to_integer <FUNCTION>to_unsigned <FUNCTION>to_signed <!-- std.textio --> <KEYWORD2>line <KEYWORD2>text <KEYWORD2>side <KEYWORD2>width <LITERAL2>left <LITERAL2>right <LITERAL2>std_input <LITERAL2>std_output <LITERAL3>input <LITERAL3>output <FUNCTION>readline <FUNCTION>writeline <!-- ieee.std_logic_textio --> <FUNCTION>oread <FUNCTION>owrite <FUNCTION>hread <FUNCTION>hwrite <!-- ieee.std_logic_arith --> <KEYWORD2>signed <KEYWORD2>unsigned <KEYWORD2>small_int <FUNCTION>conv_integer <FUNCTION>conv_unsigned <FUNCTION>conv_signed <FUNCTION>conv_std_logic_vector <FUNCTION>shl <FUNCTION>shr <FUNCTION>ext <FUNCTION>sxt <!-- ieee.math_real --> <LITERAL2>math_e <LITERAL2>math_1_over_e <LITERAL2>math_pi <LITERAL2>math_2_pi <LITERAL2>math_1_over_pi <LITERAL2>math_pi_over_2 <LITERAL2>math_pi_over_3 <LITERAL2>math_pi_over_4 <LITERAL2>math_3_pi_over_2 <LITERAL2>math_log_of_2 <LITERAL2>math_log_of_10 <LITERAL2>math_log2_of_e <LITERAL2>math_log10_of_e <LITERAL2>math_sqrt_2 <LITERAL2>math_1_over_sqrt_2 <LITERAL2>math_sqrt_pi <LITERAL2>math_deg_to_rad <LITERAL2>math_rad_to_deg <FUNCTION>sign <FUNCTION>ceil <FUNCTION>floor <FUNCTION>round <FUNCTION>trunc <FUNCTION>realmax <FUNCTION>realmin <FUNCTION>uniform <FUNCTION>sqrt <FUNCTION>cbrt <FUNCTION>exp <FUNCTION>log <FUNCTION>log2 <FUNCTION>log10 <FUNCTION>sin <FUNCTION>cos <FUNCTION>tan <FUNCTION>arcsin <FUNCTION>arccos <FUNCTION>arctan <FUNCTION>sinh <FUNCTION>cosh <FUNCTION>tanh <FUNCTION>arcsinh <FUNCTION>arccosh <FUNCTION>arctanh <!-- ieee.math_complex --> <KEYWORD2>complex <KEYWORD2>positive_real <KEYWORD2>principal_value <KEYWORD2>complex_polar <KEYWORD2>re <KEYWORD2>im <KEYWORD2>mag <KEYWORD2>arg <LITERAL2>math_cbase_1 <LITERAL2>math_cbase_j <LITERAL2>math_czero <FUNCTION>cmplx <FUNCTION>get_principal_value <FUNCTION>complex_to_polar <FUNCTION>polar_to_complex <FUNCTION>conj </KEYWORDS> </RULES> </MODE> Other jEdit examples (source code examples)Here is a short list of links related to this jEdit vhdl.xml source code file: |
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